Title :
65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS
Author :
Yamaoka, Masanao ; Maeda, Noriaki ; Shimazaki, Yasuhisa ; Osada, Kenichi
Author_Institution :
Hitachi, Tokyo
Abstract :
We design a technique to separately measure the Vth of NMOS and PMOS. This technique is used to determine the body bias of NMOS and PMOS individually. Prototype chips with 1Mb 0.51 mm2 high-density SRAM cells using a 65 nm low-power process are fabricated and achieve 1.0 V operation, even when considering actual Vth variation.
Keywords :
MOSFET; SRAM chips; low-power electronics; nanoelectronics; 3sigma systematic variation; NMOS body bias; PMOS body bias; Vth variation monitoring; low-power fabrication process; low-power high-density SRAM cells; prototype chips; size 65 nm; voltage 1.0 V; Current measurement; Immune system; Leakage current; MOS devices; MOSFETs; Monitoring; Prototypes; Random access memory; Semiconductor device measurement; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
DOI :
10.1109/ISSCC.2008.4523218
