65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS

We design a technique to separately measure the V_th of NMOS and PMOS. This technique is used to determine the body bias of NMOS and PMOS individually. Prototype chips with 1Mb 0.51 mm² high-density SRAM cells using a 65 nm low-power process are fabricated and achieve 1.0 V operation, even when considering actual V_th variation.