Title :
A functional memory based architecture for running sorting
Author :
Eldos, T. ; Mayyas, K. ; Aboulnasr, T.
Author_Institution :
Dept. of Electr. Eng., Jordan Univ. of Sci. & Technol., Irbid, Jordan
Abstract :
In real-time applications, software-level implementations of running sorting algorithms may not be able to meet the processing time requirements, particularly when the size of the running window is large. In this paper, we present a hardware running sorter based on a functional memory architecture. The proposed approach accelerates operations thus giving the new hardware the capability of completing the running sorting algorithm in log N+7 CPU cycles. Details of the architecture units are explained, and a functional description of its operation provided
Keywords :
computational complexity; memory architecture; sorting; architecture units; functional description; functional memory architecture; functional memory based architecture; hardware running sorter; real-time applications; running sorting algorithms; Acceleration; Application software; Australia; Concurrent computing; Field programmable gate arrays; Filtering; Hardware; Memory architecture; Signal processing; Sorting;
Conference_Titel :
Signal Processing and Its Applications, 1999. ISSPA '99. Proceedings of the Fifth International Symposium on
Conference_Location :
Brisbane, Qld.
Print_ISBN :
1-86435-451-8
DOI :
10.1109/ISSPA.1999.815769
