Title :
A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency
Author :
Liang, Xiaoyao ; Brooks, David ; Wei, Gu-Yeon
Author_Institution :
Harvard Univ., Cambridge, MA
Abstract :
This paper explores two fine-grained, post-fabrication circuit-tuning techniques to combat process variation for pipelined logic componentsrdquo voltage interpolation and variable latency. These techniques are applied to a single-precision floating-point unit (FPU) designed using a standard CAD synthesis flow in a 0.13 mum CMOS logic process with 8 metal layers. Measured results from fabricated chips show that both techniques provide wide frequency tuning range to deal with frequency fluctuations arising from process variations with minimal power overhead, and in some configurations, power savings.
Keywords :
CMOS logic circuits; circuit CAD; circuit tuning; floating point arithmetic; CMOS logic process; circuit-tuning technique; frequency fluctuation; pipelined logic component; process-variation-tolerant floating-point unit design; size 0.13 mum; standard CAD synthesis; variable latency; voltage interpolation; CMOS logic circuits; CMOS process; Circuit synthesis; Delay; Design automation; Frequency; Interpolation; Logic circuits; Logic design; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
DOI :
10.1109/ISSCC.2008.4523228
