A low noise Si-CMOS amplifier-multiplexer readout circuit array for imaging applications

Author

Zhu, Zhangming ; Yang, Yintang ; Meng, Qinchao

Author_Institution

Microelectron. Inst., Xidian Univ., Xi´´an

fYear

2006

fDate

Oct. 2006

Firstpage

629

Lastpage

633

Abstract

The noises of readout circuit are analyzed and methods for decreasing noises are presented in this paper. An improved readout circuit with capacitive transimpedance amplifier (CTIA) is presented, and the correlated double sampling technology is used. The structure and operational mechanism of the circuit are detailed. Using CSMC 0.6mum DPDM CMOS, the circuit is implemented. The measured results show that the output noise is only 283nV rms at the power supply voltage 5V and the bandwidth of 1MHz. The active size of readout circuits array is 8.9 times 1.4mm²

Keywords

CMOS integrated circuits; infrared imaging; integrated circuit noise; multiplexing equipment; operational amplifiers; readout electronics; sample and hold circuits; signal processing equipment; silicon; 0.6 micron; 1 MHz; 283 nV; 5 V; CSMC DPDM CMOS; Si; capacitive transimpedance amplifier; correlated double sampling; improved readout circuit; low noise CMOS amplifier-multiplexer readout circuit; noise reduction; operational mechanism; Bandwidth; CMOS technology; Circuit analysis; Circuit noise; Low-noise amplifiers; Noise measurement; Power measurement; Power supplies; Sampling methods; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306397

Filename

4098189