A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed

Author

Javanifard, Johnny ; Tanadi, Tris ; Giduturi, Hari ; Loe, Kim ; Melcher, Robert L. ; Khabiri, Shahnam ; Hendrickson, Nicholas T. ; Proescholdt, Andrew D. ; Ward, David A. ; Taylor, Mark A.

Author_Institution

Intel, Folsom, CA

fYear

2008

fDate

3-7 Feb. 2008

Firstpage

424

Lastpage

624

Abstract

Advancing to 45 nm 1 Gb NOR flash requires new process and design techniques. The process developments of SACS, tungsten source rail, and better pump capacitors increase cell size and reduce overall die size. The design techniques of two-transistor row decoders, a new sensing architecture, more effective charge pumps and program performance improvements enable multilevel flash cells to meet a die size of 30 mm² and 5 MB/s program speed in 45 nm technology.

Keywords

NOR circuits; capacitors; decoding; flash memories; multivalued logic circuits; transistor circuits; tungsten; NOR flash; SAC process architecture; byte rate 5 MByte/s; cell size reduction; multilevel flash cells; overall die size reduction; pump capacitors; self-aligned-contact process; size 45 nm; tungsten source rail; two-transistor row decoders; Capacitance; Charge pumps; Circuits; Decoding; Flash memory; MOS capacitors; Nonvolatile memory; Rails; Tungsten; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4244-2010-0

Electronic_ISBN

978-1-4244-2011-7

Type

conf

DOI

10.1109/ISSCC.2008.4523238

Filename

4523238