Title :
The evolution of the HP/Convex Exemplar
Author :
Brewer, T. ; Astfalk, G.
Author_Institution :
Convex Div., Hewlett-Packard Co., Richardson, TX, USA
Abstract :
The Exemplar X-Class is the second generation SPP from HP/Convex. It is a ccNUMA (cache coherent nonuniform memory access) architecture comprised of multiple nodes. We describe the evolution from the first generation systems to the current S- and X-class systems. Each node may contain up to 16 PA-8000 processors, 16 Gbytes of memory and 8 PCI busses. The peak performance of each node is 11.5 Gflops. Memory access is UMA within each node and is accomplished via a nonblocking crossbar. Each node can be correctly considered as a symmetric multiprocessor. The interconnect between nodes is a derivative of the IEEE standard, SCI, which permits up to 32 nodes to be connected in a 2 dimensional topology. The system includes features to aid high performance engineering/scientific computations. Among these are a hardware bcopy engine, interconnect caches, and memory and cache based semaphores.
Keywords :
cache storage; parallel architectures; parallel machines; storage management; system buses; 2 dimensional topology; Exemplar X-Class; HP/Convex Exemplar evolution; IEEE standard SCI; PA-8000 processors; PCI busses; S-class systems; X-class systems; cache based semaphores; cache coherent nonuniform memory access architecture; ccNUMA; first generation systems; hardware bcopy engine; high performance engineering/scientific computations; interconnect caches; multiple nodes; nonblocking crossbar; second generation SPP; symmetric multiprocessor; Application specific integrated circuits; Bandwidth; Engines; Hardware; Logic arrays; Memory architecture; Power generation; System buses; Topology; Workstations;
Conference_Titel :
Compcon '97. Proceedings, IEEE
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-7804-6
DOI :
10.1109/CMPCON.1997.584677
