Hardware architecture for H.264/AVC intra 16×16 frame processing

Author

Loukil, H. ; Arous, S. ; Werda, I. ; Ben Atitallah, Ahmed ; Kadionik, P. ; Masmoudi, N.

Author_Institution

Nat. Sch. of Eng., Univ. of Sfax, Sfax

fYear

2009

fDate

23-26 March 2009

Firstpage

1

Lastpage

5

Abstract

In this paper, we present an efficient H.264 / AVC intra 16times16 frame coder system. The system achieves real-time performance for video conference applications. The INTRA 16times16 is composed by intra 16times16 prediction, integer transform, quantization AC, inverse quantization AC, quantization DC, hadamard, inverse quantization DC, and inverse integer transform. The proposed hardware is implemented in VHDL. The VHDL RTL code works at 160 MHz in an Altera Stratix II FPGA and it code 129 Mpixels per second. This work will be used as an intellectual property (IP) integrated in H.264/AVC encoder.

Keywords

Hadamard transforms; field programmable gate arrays; industrial property; video codecs; video coding; FPGA; H.264/AVC; Hadamard transform; VHDL; hardware architecture; integer transform; intellectual property; intra 16times16 frame processing; intra-frame coder system; inverse integer transform; inverse quantization AC; quantization AC; Automatic voltage control; Computer architecture; Field programmable gate arrays; Hardware; Intellectual property; Laboratories; Prediction algorithms; Quantization; Timing; Videoconference; H.264; Hardware Implementation; VHDL; integer transform; intra prediction; quantization;

fLanguage

English

Publisher

ieee

Conference_Titel

Systems, Signals and Devices, 2009. SSD '09. 6th International Multi-Conference on

Conference_Location

Djerba

Print_ISBN

978-1-4244-4345-1

Electronic_ISBN

978-1-4244-4346-8

Type

conf

DOI

10.1109/SSD.2009.4956671

Filename

4956671