DocumentCode
3465757
Title
Memory technologies for 50 nm and beyond
Author
Kim, Kinam
Author_Institution
Semicond. R&D Div., Samsung Electron. Co. Ltd, Kyunggi-Do
fYear
2006
fDate
Oct. 2006
Firstpage
685
Lastpage
688
Abstract
This paper discusses whether memory technologies can continue to evolve to 50 nm node and beyond for DRAM, NAND flash and emerging new nonvolatile RAMs. First, barriers to overcome technological challenges will be addressed for those memories. Second, technological solutions against the quandaries will be discussed in detail. It is expected beyond 30 nm technology node that novel memory scheme with a 3-dimensional structure is prevailing upon both logic and memory array along with the development of new materials and new device structures
Keywords
DRAM chips; NAND circuits; flash memories; nanotechnology; 30 nm; 3D structure; 50 nm; DRAM; NAND flash; logic memory array; memory technologies; nonvolatile RAM; Electrodes; FinFETs; High K dielectric materials; High-K gate dielectrics; Leakage current; Logic arrays; MIM capacitors; Metal-insulator structures; Random access memory; Tin;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location
Shanghai
Print_ISBN
1-4244-0160-7
Electronic_ISBN
1-4244-0161-5
Type
conf
DOI
10.1109/ICSICT.2006.306437
Filename
4098207
Link To Document