Title :
A 1ps-Resolution 2ns-Span 10Gb/s Data-Timing Generator with Spectrum Conversion
Author :
Kawamura, Tomoaki ; Ohtomo, Yusuke ; Nishimura, Kazuyoshi ; Ishihara, Noboru
Author_Institution :
NTT, Atsugi
Abstract :
The DTG discussed in this paper, reduces data-dependent jitter (DDJ) and offers ns-order delay span for input data rates of up to 11Gb/s. The fine-delay blocks consist of 6 sub-blocks. Total fine delay is adjusted by combining the delays of the 6 sub-blocks using the control inputs for the fine-delay block. NMOS transistors are used as the variable capacitors (VCs) for delay control, because they provide small capacitance of <50fF that makes it possible to generate sub- ps delay. Since the DTG uses a spectrum-conversion technique that suppresses the effect of the group-delay deviation of the delay gates, its output jitter is reduced to one-third that of a conventional DTG
Keywords :
MOSFET; capacitors; delays; jitter; NMOS transistors; bit rate 10 Gbit/s; data-dependent jitter; data-timing generator; delay control; fine-delay blocks; group-delay deviation effect; output jitter; spectrum-conversion technique; variable capacitors; Bandwidth; Capacitance; Circuit simulation; Delay effects; Frequency; Jitter; Optical signal processing; Propagation delay; Repeaters; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
DOI :
10.1109/ISSCC.2008.4523254
