A 1.8W 115Gb/s Serial Link for Fully Buffered DIMM with 2.1ns Pass-Through Latency in 90nm CMOS

Author

Pfaff, Dirk ; Kanesapillai, Sivakumar ; Yavorskyy, Volodymyr ; Carvalho, Carlos ; Yousefi, Reza ; Khan, Muhammad Ali ; Monson, Trevor ; Ayoub, Mark ; Reitlingshoefer, Claus

Author_Institution

Diablo Technol., Gatineau, ON

fYear

2008

fDate

3-7 Feb. 2008

Firstpage

462

Lastpage

628

Abstract

In this paper, a low-latency low-power high-speed serial link for FBDIMM is reported. A total of 24 transceivers, each running at 4.8 Gb/s, form the core of the link which is completed by a CMU. Each transceiver features a quarter-rate receive front-end and a quarter-rate transmit backend. Standard CMOS logic performs receive de-multiplexing and transmit multiplexing. Temporary drift of the receive data stream is absorbed by a programmable elastic buffer (FIFO). Retimed receive data is directly forwarded to the transmit multiplexer in pass-through mode. FBDIMM systems potentially increase the memory latency.

Keywords

CMOS logic circuits; CMOS memory circuits; buffer storage; low-power electronics; transceivers; bit rate 115 Gbit/s; demultiplexing; fully buffered DIMM; low-latency low-power high-speed serial link; multiplexing; pass-through mode; power 1.8 W; programmable elastic buffer; size 90 nm; standard CMOS logic; transceiver; Bandwidth; Clocks; Delay; Energy consumption; Fabrics; Jitter; Phase measurement; Switches; Transceivers; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4244-2010-0

Electronic_ISBN

978-1-4244-2011-7

Type

conf

DOI

10.1109/ISSCC.2008.4523257

Filename

4523257