Scaling considerations for sub-90 nm split-gate flash memory cells

The increasing usage of flash memory in mobile applications is pushing the scaling limit of Flash memory technology. This paper presents a systematic scaling methodology, architecture, optimization strategy, and performance of sub-90 nm split-gate flash memory cells. The device simulation results show that the split-gate cells can be scaled to 90 nm node and below using shallow source/drain junctions and a highly localized source-halo in conjunction with channel engineering. Using properly optimized technology parameters, sub-90 nm cells with tolerable leakage current and efficient time-to-program and time-to-erase can be achieved