DocumentCode
3466057
Title
A 39.1-to-41.6GHz ΔΣ Fractional-N Frequency Synthesizer in 90nm CMOS
Author
Pellerano, Stefano ; Mukhopadhyay, Rajarshi ; Ravi, Adit ; Laskar, Joy ; Palaskas, Yorgos
Author_Institution
Intel, Hillsboro, OR
fYear
2008
fDate
3-7 Feb. 2008
Firstpage
484
Lastpage
630
Abstract
In this paper, we present a 39.1-to-41.6 GHz 1.2 V 64 mW DeltaSigma fractional-N frequency synthesizer that is implemented in 90nm CMOS. To reduce power consumption, a divide-by-4 injection-locking frequency divider (ILFD) is used in the feedback loop and a digital calibration technique is implemented to overcome the ILFD locking-range limitations.
Keywords
CMOS integrated circuits; MIMIC; delta-sigma modulation; frequency dividers; frequency synthesizers; millimetre wave frequency convertors; CMOS technology; MIMIC; delta-sigma convertors; digital calibration; feedback loop; fractional-N frequency synthesizer; frequency 39.1 GHz to 41.6 GHz; injection-locking frequency divider; power 64 mW; size 90 nm; voltage 1.2 V; Bandwidth; Calibration; Energy consumption; Frequency conversion; Frequency measurement; Frequency synthesizers; Phase locked loops; Phase noise; Voltage control; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
Print_ISBN
978-1-4244-2010-0
Electronic_ISBN
978-1-4244-2011-7
Type
conf
DOI
10.1109/ISSCC.2008.4523268
Filename
4523268
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