Novel Device Structures for Charge Trap Flash Memories

Demands for the high-density non-volatile memory products have been growing explosively. For further scaling of flash memory devices, however, the currently-dominant poly-silicon floating gate structures show several limitations, and novel structures based on charge traps are emerging as a strong contender. We present nanoscale charge trap flash memory devices for 64Gb and beyond. We have developed a sidewall spacer patterning method and its multiplication technique. Utilizing these techniques, we have fabricated and characterized 30-nm-long channel NAND cell structures and 80-nm-long channel double bit NOR cell structures. In addition, we propose an arch gate structure for NAND application and a vertical channel structure for double bit NOR application