Window rip-up for faster testing and fault tolerance in FPGAs

In this paper we present a window based rip-up strategy for incrementally routing signal nets on Field Programmable Gate Arrays (FPGAs). In our strategy we use a variable size window to reduce the problem size when incrementally routing fault tolerant (FT) FPGA circuits. Our methods are suitable for standard FPGA routers as well as specialized routers used to incrementally route circuits in Adaptive Computing Systems (ACSs). We demonstrate our technique on a FPGA based, on-line ACS that is implemented with the ORCA© FPGA available from Lucent Technologies. The effectiveness of the technique for system configuration generation and its associated impact is evaluated across four benchmark circuits programmed on the ORCA 2C FPGA. The results show up to 65.5% reduction in router CPU time and 63.8% reduction in configuration file size