Title :
A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation
Author :
Hsiao, Keng-Jan ; Lee, Tai-Cheng
Author_Institution :
Nat. Taiwan Univ., Taipei
Abstract :
A low-jitter distributed DLL for multiple-phase clock generation is proposed. The distributed DLL monitors the phase difference for each output clock and the reference clock. This distributed DLL is fabricated in a 90 nm CMOS process and consumes 15 mW from a 1 V supply excluding output buffers. The distributed DLL operates from 8 to 10 GHz, which is consistent with the simulation results and also the fastest in CMOS technology.
Keywords :
CMOS digital integrated circuits; clocks; delay lock loops; jitter; microwave integrated circuits; CMOS process; CMOS technology; frequency 8 GHz to 10 GHz; low-jitter distributed DLL; multiple-phase clock generation; phase difference; power 15 mW; size 90 nm; voltage 1 V; CMOS technology; Capacitors; Clocks; Delay effects; Delay lines; Frequency; Inverters; Jitter; Partial discharges; Solid state circuits;
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
DOI :
10.1109/ISSCC.2008.4523283
