Discussion on the CHE Programming Characteristics with the Scaling Down of Charge Trapping Flash Memory

The scaling down issues in the charge trapping memory are investigated in this work. In the sub-100 nm devices, the punch-through problem, as well as high program voltage and electrical field limitation are studied by device simulation and measurement. The authors found CHE program mechanism meet certain limitation in the future short channel devices. Furthermore, program induced charge distribution is extracted by a charge pumping method, and the related problems to the multi-bit application is discussed