DocumentCode
3466574
Title
Circuits and Implementation of a Low-Power Embedded EEPROM Memory
Author
Dong-Sheng, Liu ; Xue-cheng, Zou ; Fan, Zhang ; Min, Deng
Author_Institution
Dept. of Electron. Sci. & Technol., Huazhong Univ. of Sci., Wuhan
fYear
2006
fDate
23-26 Oct. 2006
Firstpage
836
Lastpage
838
Abstract
A 2-Kbit low-power embedded EEPROM memory, which is based on SMIC 0.35 mum three-metal two-poly mixed signal CMOS technology with embedded EEPROM technology, has been developed. Key design techniques of power dissipation optimization for EEPROM memory are described. Optimizations of the current consumption for the charge pump circuit are treated in this paper. To optimize the read access power consumption, a new SA (sense amplifier) using voltage sensing is proposed
Keywords
CMOS integrated circuits; EPROM; embedded systems; low-power electronics; 0.35 micron; charge pump circuit; current consumption; low-power embedded EEPROM memory; power dissipation optimization; sense amplifier; three-metal two-poly mixed signal CMOS technology; CMOS technology; Charge pumps; Circuits; Design optimization; EPROM; Power amplifiers; Power dissipation; Read-write memory; Signal processing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location
Shanghai
Print_ISBN
1-4244-0160-7
Electronic_ISBN
1-4244-0161-5
Type
conf
DOI
10.1109/ICSICT.2006.306523
Filename
4098250
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