• DocumentCode
    3466636
  • Title

    Dual chip memory package

  • Author

    Kweon, Young-Do ; Ahn, Sexing-Ho ; Sohn, Hae-Jeong ; Song, Young-Hee ; Oh, Se-Yong

  • Author_Institution
    Samsung Electron. Co., Kiheung, South Korea
  • fYear
    1995
  • fDate
    2-4 Oct 1995
  • Firstpage
    127
  • Lastpage
    132
  • Abstract
    Today´s computer systems require more main memories than before due to the development of heavy-load softwares and the integration of multiple functions in a computer. However, since the computers became portable the sizes of computers are getting smaller. This means that it is necessary to put more memory chips into a limited space of the computers. In order to fulfil above requirement, a new high density package was developed, which looked the same as conventional plastic packages outside, and contained two chips inside, and named the Dual Chip Package (DCP). In packaging two chips in a package outline, chip-on-tape (COT) technology was combined with lead frames. The tape had wiring patterns inside and interconnection tabs along the periphery of the tape. The lead frames for the DCP were prepared by bonding the inner leads of the lead frames to the interconnection tabs of the tapes. Two chips are attached to the top side and the bottom side of the tape, and wire-bonded onto the tape surface. In the chip attachment and wire bonding process, one side of the tape was coated with an epoxy encapsulant to protect the chips during the wire bonding of the other side. After this process, the assembly processes were the same as those of conventional plastic packages. With DCP, it is possible to change the pin configurations of the package by varying the design of the tape. Reliability tests showed that the DCP met JEDEC level 3 requirement in pre-conditioning tests
  • Keywords
    encapsulation; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; integrated memory circuits; lead bonding; wiring; JEDEC level 3 requirement; chip-on-tape technology; dual chip memory package; epoxy encapsulant; high density package; interconnection tabs; lead frames; pin configurations; pre-conditioning tests; reliability tests; wire bonding process; wiring patterns; Assembly; Bonding; Bonding processes; Electronics packaging; Flexible printed circuits; Integrated circuit interconnections; Integrated circuit packaging; Packaging machines; Plastic integrated circuit packaging; Plastic packaging; Portable computers; Protection; Space technology; Testing; Thick film circuits; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Manufacturing Technology Symposium, 1995. 'Manufacturing Technologies - Present and Future', Seventeenth IEEE/CPMT International
  • Conference_Location
    Austin, TX
  • Print_ISBN
    0-7803-2996-1
  • Type

    conf

  • DOI
    10.1109/IEMT.1995.526104
  • Filename
    526104