DocumentCode
3466661
Title
A 24GS/s 6b ADC in 90nm CMOS
Author
Schvan, Peter ; Bach, Jerome ; Fait, C. ; Flemke, Philip ; Gibbins, Robert ; Greshishchev, Yuriy ; Ben-Hamida, Naim ; Pollex, Daniel ; Sitch, John ; Wang, Shing-Chi ; Wolczanski, John
Author_Institution
Nortel, Ottawa, ON
fYear
2008
fDate
3-7 Feb. 2008
Firstpage
544
Lastpage
634
Abstract
This paper presents a 24 GS/s 6 b ADC in 90 nm CMOS with the highest ENOB up to 12 GHz input frequency and lowest power consumption of 1.2 W compared to ADCs with similar performance. It uses an interleaved architecture of SAR type self-calibrating converters operating from 1 V supply combined with an array of 2.5 V T/Hs with delay, gain and offset-calibration capability.
Keywords
CMOS integrated circuits; analogue-digital conversion; low-power electronics; ADC; CMOS process; SAR architecture; analog-digital conversion; converters; frequency 12 GHz; power consumption; size 90 nm; Calibration; Circuits; Clocks; Field programmable gate arrays; Frequency estimation; Jitter; Packaging; Sampling methods; Signal sampling; Yield estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
Print_ISBN
978-1-4244-2010-0
Electronic_ISBN
978-1-4244-2011-7
Type
conf
DOI
10.1109/ISSCC.2008.4523298
Filename
4523298
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