Title :
A 64/spl times/64-bit modified Booth multiplier utilizing multiplexer-select Booth encoder
Author :
Wu, Xinyu ; Huang, Chi ; Lai, Jinmei ; Sun, Chenshou
Author_Institution :
State Key Lab of ASIC & Syst., Fudan Univ., Shanghai
Abstract :
In this paper, we describe a 64times64-bit high performance multiplier based on multiplexer cells which is implemented with pass transistor logic. A multiplexer-select Booth encoders was developed to increase speed and reduce the hardware cost. Moreover, a partitioned method was introduced in the design to save the propagate time of final adder. Realistic simulation using extracted timing parameters from the layout shows that the propagation time of the critical path is 2.82ns at 1.8V on 0.18mum CMOS technology
Keywords :
CMOS logic circuits; adders; encoding; integrated circuit layout; logic partitioning; multiplexing equipment; multiplying circuits; 0.18 micron; 1.8 V; 2.82 ns; Booth multiplier; CMOS technology; adder; critical path; multiplexer-select Booth encoders; partitioning method; pass transistor logic; propagation time; timing parameters; Adders; CMOS logic circuits; Costs; Delay; Design methodology; Encoding; Hardware; Multiplexing; Signal processing algorithms; Timing;
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location :
Shanghai
Print_ISBN :
0-7803-9210-8
DOI :
10.1109/ICASIC.2005.1611268
