Title :
High speed radix-16 design of a scalable Montgomery multiplier
Author :
Fan, Yibo ; Zeng, Xiaoyang ; Yu, Yu ; Wang, Gang ; Deng, Huang ; Zhang, Qianling
Author_Institution :
State-Key Lab. of ASIC & Syst., Fudan Univ., Shanghai
Abstract :
This paper describes an improved version of the Tenca-Todorov-Koc word based radix-8 Montgomery multiplier. It uses radix-16 for fast without adding any hardware, and adjusting the data-path to get shorter critical path, and requires half of FIFO memory. This design is reconfigurable to accept any input precision as the Tenca-Todorov-Koc´s design. An ASIC implementation in 0.25 mum CMOS standard cell technology can perform 2048-bit modular exponentiation in 28ms under 125MHz clock period
Keywords :
CMOS logic circuits; application specific integrated circuits; digital arithmetic; high-speed integrated circuits; integrated circuit design; logic design; multiplying circuits; 0.25 micron; 125 MHz; 2048 bit; 28 ms; ASIC implementation; CMOS standard cell technology; FIFO memory; Tenca-Todorov-Koc design; Tenca-Todorov-Koc word based multiplier; high speed radix-16 design; radix-8 Montgomery multiplier; scalable Montgomery multiplier; Application software; Application specific integrated circuits; Authentication; CMOS technology; Clocks; Digital signatures; Hardware; Public key cryptography; Timing; Web and internet services;
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location :
Shanghai
Print_ISBN :
0-7803-9210-8
DOI :
10.1109/ICASIC.2005.1611286
