Experimental implementation of DPA attacks on AES design with Flash-based FPGA technology

In this paper, authors conducted a successful differential power analysis DPA attack on an Advanced Encryption Standard AES hardware implementation on Flash-based FPGA technology. Correlation analysis method is used to reduce DPA attack data processing time. It is chosen between three methods analysing power consumption on DPA attacks. An experimental set-up is defined to implement on an FPGA board critical AES modules and DPA attack. As main contribution, this work proved the success of DPA attack on Flash-based FPGA. Experimental results showed that for different secret key values a maximum of correlation with the correct key is obtained during 20 mn of data processing time.