A low-power complementary pass-transistor tree multiplier based on adiabatic 4-2 compressors

This paper describes a low-power tree multiplier based on adiabatic logic. It is composed of three parts: a partial-product generator, a partial-product compression tree (Wallace tree), and a final carry-lookahead adder. Adiabatic 4-2 compressors are used to construct the Wallace tree. All the circuits use complementary pass-transistor adiabatic logic (CPAL) circuits to recover the charge of node capacitances. The simulation results show that the CPAL tree multiplier achieves considerable energy savings.