DocumentCode
3468158
Title
A fast locking charge-pump PLL with adaptive bandwidth
Author
Ge, Yan ; Feng, Wennan ; Chen, Zhongjian ; Jia, Song ; Ji, Lijiu
Author_Institution
Inst. of Microelectron., Peking Univ., Beijing
Volume
1
fYear
2005
fDate
24-0 Oct. 2005
Firstpage
383
Lastpage
386
Abstract
Design of bandwidth adaptive phase-locked loops (PLL) to achieve fast locking is presented in this paper. The proposed topology uses only one adaptive phase frequency detector (PFD) and controllable charge pumps to realize adaptive bandwidth scheme. With a SMIC standard 0.25mum 1P5M 2.5V CMOS logic process, the measured results show that the experimental chip has properties of fast locking less than 4 mus and low power consumption about 18mW
Keywords
CMOS integrated circuits; low-power electronics; network topology; phase detectors; phase locked loops; trigger circuits; 0.25 micron; 2.5 V; CMOS logic process; adaptive bandwidth; adaptive phase frequency detector; controllable charge pumps; fast locking time; phase locked loops; Adaptive control; Bandwidth; CMOS logic circuits; CMOS process; Charge pumps; Measurement standards; Phase frequency detector; Phase locked loops; Programmable control; Topology; PLL; adaptive bandwidth; dual-edge-triggered PFD; fast locking;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location
Shanghai
Print_ISBN
0-7803-9210-8
Type
conf
DOI
10.1109/ICASIC.2005.1611343
Filename
1611343
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