A parallel processing architecture for FSS block-matching motion estimation

Author

Dhahri, Slim ; Zitouni, Abdelkader ; Tourki, Rached

Author_Institution

Electron. & Micro-Electron. Lab. (LABIT06), Univ. of Gafsa, Gafsa, Tunisia

fYear

2011

fDate

3-5 March 2011

Firstpage

1

Lastpage

5

Abstract

Motion Estimation (ME) is a key factor for achieving enhanced compression ratio. However, ME involves high computational complexity. The main goal is to reduce the execution time without reducing image quality. In this paper, a proposed high parallel processing architecture is presented for four-step search block-matching motion estimation. The proposed method develops an architecture which using 9 processing-elements (PE) and processes them in parallel. The architecture has been simulated and synthesized with VHDL and ASIC (CMOS 45nm). Synthesize results show that the proposed architecture achieves a high performance for real time motion estimation.

Keywords

computational complexity; data compression; image matching; image processing equipment; motion estimation; parallel processing; ASIC; CMOS; FSS block matching motion estimation; VHDL; compression ratio enhancement; computational complexity; four step search block matching motion estimation; high parallel processing architecture; real time motion estimation; Clocks; Computer architecture; Delay; Frequency selective surfaces; Logic gates; Motion estimation; Parallel processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Computing and Control Applications (CCCA), 2011 International Conference on

Conference_Location

Hammamet

Print_ISBN

978-1-4244-9795-9

Type

conf

DOI

10.1109/CCCA.2011.6031442

Filename

6031442