Design of future single wafer logic fabs

Author

Castrucci, Paul

Author_Institution

Paul Castrucci & Assoc. Inc., Cambridge, MA, USA

fYear

1995

fDate

2-4 Oct 1995

Firstpage

283

Lastpage

285

Abstract

Describes several unique, single wafer, logic fabs designed to meet the challenges of wafer processing in the 1990s. Specifically, the author compares four fab designs: (1) a new fab standard (NFS), which is designed with minienvironment Class 1 or better in the wafer processing and Class 10,000 in the support areas; (2) a more conventional Class 1 ball-room design that is smaller due to new tooling concepts; (3) a unique minienvironment, small footprint, three story production fab in which the subfloor is used for photo lithography and ion implant; (4) and a minienvironment, two story production fab, slab-on-grade design. The four fab designs will produce a minimum of 25 logic part numbers per day and will process 200 mm, 0.35 micron technology wafers at a rate of 500 wafer starts per day with four levels of metal in seven days or less

Keywords

VLSI; integrated circuit yield; ion implantation; photolithography; technological forecasting; Class 10,000; ball-room design; fab standard; ion implant; minienvironment Class 1; photolithography; single wafer logic fabs; slab-on-grade design; three story production fab; tooling concepts; wafer processing; Costs; Design engineering; Floors; Ice; Implants; Integrated circuit technology; Lithography; Logic design; Production; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Manufacturing Technology Symposium, 1995. 'Manufacturing Technologies - Present and Future', Seventeenth IEEE/CPMT International

Conference_Location

Austin, TX

Print_ISBN

0-7803-2996-1

Type

conf

DOI

10.1109/IEMT.1995.526127

Filename

526127