Title :
Statistical Compact Modeling and Si Verification Methodology
Author :
Wason, Vineet ; An, Judy ; Goo, Jung-Suk ; Wu, Zhi-Yuan ; Chen, Qiang ; Thuruthiyil, Ciby ; Topaloglu, Rasit ; Chiney, Priyanka ; Ali, Icel
Author_Institution :
Adv. Micro Devices, Sunnyvale, CA
Abstract :
As we scale down to sub-65nm technologies, transistors and interconnects no longer act as predictable elements, but start acting as statistical blocks due to static and dynamic variations. This invited paper first reviews some of the key variations that need to be considered for any statistical analysis. Also, details for implementing statistical models into compact modeling flow are discussed. Finally, the paper reviews one of the techniques used for generating and validating statistical models with the silicon data
Keywords :
semiconductor device models; statistical analysis; silicon data; silicon verification methodology; statistical analysis; statistical compact modeling; sub-65nm technology; Doping; Fluctuations; Integrated circuit interconnections; Integrated circuit technology; MOSFET circuits; Predictive models; Silicon; Statistical analysis; Threshold voltage; Transistors;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306096
