Compact modeling of on-chip ESD protection using standard MOS and BJT models

SPICE type simulation using compact models is a very useful tool for predicting circuit performance under ESD stress conditions. However device models valid in the ESD current/voltage operating region are not widely available. This paper starts with a brief description of compact modeling for ESD devices working in snapback mode. A practical macro modeling approach for modeling snapback of MOS and LVSCR is then introduced. It uses advanced industry standard BJT and MOS models. This method´s advantages are simplicity, high simulation speed, wider availability, and reduced convergence issues