Title :
Framework for massively parallel testing at wafer and package test
Author :
Baba, A. Hakan ; Kim, Kee Sup
Author_Institution :
Stanford Univ., Stanford, CA, USA
Abstract :
A novel DFT approach is introduced that enables massively parallel testing of logic devices at both wafer and package test. Parallelism is achieved by utilizing interconnection networks that are built onto a wafer probe or a tester interface unit. The financial benefits of this method in a realistic setting are also presented.
Keywords :
design for testability; wafer level packaging; wafer-scale integration; design for testability; interconnection networks; logic device testing; massively parallel testing; package test; parallelism; tester interface unit; wafer probe; wafer test; Circuit testing; Hardware; Logic devices; Logic testing; Multiprocessor interconnection networks; Packaging; Pins; Probes; System testing; Very large scale integration;
Conference_Titel :
Computer Design, 2009. ICCD 2009. IEEE International Conference on
Conference_Location :
Lake Tahoe, CA
Print_ISBN :
978-1-4244-5029-9
Electronic_ISBN :
1063-6404
DOI :
10.1109/ICCD.2009.5413134
