Title :
A low-voltage low-power CMOS sample-and-hold circuit
Author :
Xiao-yan, Zheng ; Shu-bao, Guo ; Jiang, Wang ; Yu-lin, Qiu
Author_Institution :
Inst. of Microelectron., Chinese Acad. of Sci., Beijing
Abstract :
A low power supply sample-and-hold circuit for a pipelined analog-to-digital converter is described. Several approaches have been used to reduce the power consumption, including a gain-compensated structure and a simple optimum allocation of settling time parameter. To reduce the nonlinear error of the sampling switch, a signal dependent clock bootstrapping system is used. Simulation results demonstrate that the S/H circuit consumes only 2.3 mWat 1.8v supply with an accuracy of 10bit and a sampling rate of 50M
Keywords :
CMOS analogue integrated circuits; analogue-digital conversion; bootstrap circuits; low-power electronics; sample and hold circuits; 1.8 V; 2.3 mW; CMOS sample-and-hold circuit; clock bootstrapping system; nonlinear error; pipelined analog-to-digital converter; sampling switch; Analog circuits; Clocks; Digital circuits; Energy consumption; Operational amplifiers; Power supplies; Sampling methods; Switches; Switching circuits; Voltage;
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location :
Shanghai
Print_ISBN :
0-7803-9210-8
DOI :
10.1109/ICASIC.2005.1611388
