Title :
Impact of Process variations on Leakage Power in CMOS Circuits in Nano Era (Invited paper)
Author :
Chandorkar, A.N. ; Ragunandan, Ch. ; Agashe, Pradyumna ; Sharma, Dinesh ; Iwai, Hiroshi
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Mumbai
Abstract :
In sub 90 nm CMOS technology the process variations seriously affect the performance specification for leakage power and delay. In this paper, we have analyzed the techniques to improve the design quality for power and performance sensitivity to process variations. At gate level forced stacking not only reduces leakage but also improves the robustness of the gate to process variations. Logic style level the variation of leakage current with the Vth variation for various logic styles is studied
Keywords :
CMOS logic circuits; leakage currents; CMOS circuits; forced stacking; leakage current; leakage power; process variations; CMOS process; CMOS technology; Circuits; Delay estimation; Leakage current; Logic; Paper technology; Predictive models; Robustness; Threshold voltage;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306105
