Design of a DLL-gated 1.25G clock synthesizer for impulse UWB system

Author

Chen, Chen ; Liu, Boan

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing

Volume

2

fYear

2005

fDate

24-0 Oct. 2005

Firstpage

591

Lastpage

594

Abstract

This paper present a delay-locked loop (DLL) based 1.25GHz CMOS clock synthesizer for impulse ultrawideband (UWB) wireless communication system. Two DLLs are applied in the synthesizer that outputs a 1.25GHz high frequency clock and a 625MHz 16-phase clock from a 125MHz reference input. Improvement on the charge pump decreases the static phase error and novel self-tuning edge combiner eliminates the deviation caused by process variation. This clock synthesizer gives good performance on different conditions of SMIC 0.18mum CMOS process with 1.8V power supply. The simulated static phase error is 8.9ps, the peak-to-peak jitter is 10.1ps, and the centre frequency is automatically tuned to 1.25 GHz with 30% process variation presence

Keywords

CMOS integrated circuits; UHF integrated circuits; clocks; delay lock loops; ultra wideband communication; 0.18 micron; 1.25 GHz; 1.8 V; 125 MHz; 625 MHz; CMOS clock synthesizer; charge pump; delay-locked loop; impulse UWB system; impulse ultra-wideband communication; self-tuning edge combiner; static phase error; wireless communication; CMOS process; Charge pumps; Clocks; Delay; Frequency conversion; Jitter; Phase locked loops; Synthesizers; Transceivers; Wireless communication; DLL; charge pump; clock synthesizer; self-tuning;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2005. ASICON 2005. 6th International Conference On

Conference_Location

Shanghai

Print_ISBN

0-7803-9210-8

Type

conf

DOI

10.1109/ICASIC.2005.1611399

Filename

1611399