• DocumentCode
    3469234
  • Title

    3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis

  • Author

    Al Maashri, Ahmed ; Sun, Guangyu ; Dong, Xiangyu ; Narayanan, Vijay ; Xie, Yuan

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Penn State Univ., University Park, PA, USA
  • fYear
    2009
  • fDate
    4-7 Oct. 2009
  • Firstpage
    254
  • Lastpage
    259
  • Abstract
    Graphics Processing Units (GPUs) offer tremendous computational and processing power. The architecture requires high communication bandwidth and lower latency between computation units and caches. 3D die-stacking technology is a promising approach to meet such requirements. To the best of our knowledge no other study has investigated the implementation of 3D technology in GPUs. In this paper, we study the impact of stacking caches using the 3D technology on GPU performance. We also investigate the benefits of using 3D stacked MRAM on GPUs. Our work includes cost, power, and thermal analysis of the proposed architectural designs. Our results show a 53% geometric mean performance speedup for iso-cycle time architectures and about 19% for iso-cost architectures.
  • Keywords
    cache storage; microprocessor chips; 3D GPU architecture; 3D die-stacking technology; 3D stacked MRAM; architectural designs; cache stacking; caches; graphics processing units; iso-cost architectures; iso-cycle time architectures; thermal analysis; Bandwidth; CMOS technology; Computer architecture; Costs; Delay; Energy consumption; Graphics; Performance analysis; Power engineering computing; Stacking;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design, 2009. ICCD 2009. IEEE International Conference on
  • Conference_Location
    Lake Tahoe, CA
  • ISSN
    1063-6404
  • Print_ISBN
    978-1-4244-5029-9
  • Electronic_ISBN
    1063-6404
  • Type

    conf

  • DOI
    10.1109/ICCD.2009.5413147
  • Filename
    5413147