Modeling the MOSFETs´ Gate Current with the Drawn Dimensions

Author

Yeh, Chun-Chia ; Neih, Chun-Feng ; Chen, Yen-Yu ; Gong, Jeng

Author_Institution

Inst. of Electron. Eng., Nat. Tsing-Hua Univ., Hsinchu

fYear

2006

fDate

23-26 Oct. 2006

Firstpage

1287

Lastpage

1289

Abstract

A mathematical method of modeling the gate leakage current IG is presented in this work. Both the shallow trench isolation effect and the source drain extension effect on IG are included. With suitably chosen transistor dimensions the parameter extraction can be performed with the devices´ drawn size, the effective device length and width is not necessary in this model. The extracted parameters were used to predict IG of devices with other dimensions. The error between calculated results and measured results is about 3%

Keywords

MOSFET; leakage currents; semiconductor device models; MOSFET; drawn dimensions; gate leakage current; shallow trench isolation; source drain extension effect; Dielectric devices; Dielectric measurements; Integrated circuit modeling; Lead compounds; Leakage current; MOSFETs; Mathematical model; Parameter extraction; Semiconductor devices; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306116

Filename

4098385

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3469236