Title :
Design and verification of CMOS HSTL buffers - YF/spl I.bar/HSTL018
Author :
Gao, Shaoquan ; Chen, Jihua ; Ma, Jianwu ; Liu, Ting
Author_Institution :
Sch. of Comput. Sci., Nat. Univ. of Defense Technol., Changsha
Abstract :
HSTL level standard is technology for high-speed data transmission. Based on the analysis of applications, a couple of I/O buffers named YF_HSTL018, which are fully complied with HSTL level specification, are designed. The layout of the circuit is also realized. Through the Hspice simulation and chip test, good performance of the I/O buffers is demonstrated
Keywords :
CMOS logic circuits; buffer circuits; logic design; CMOS HSTL buffers; HSTL level specification; Hspice simulation; YF_HSTL018 I/O buffers; high speed transceiver logic; high-speed data transmission; Bonding; CMOS logic circuits; CMOS technology; Circuit simulation; Circuit testing; Coupling circuits; MOSFET circuits; Resistors; Transconductance; Voltage;
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location :
Shanghai
Print_ISBN :
0-7803-9210-8
DOI :
10.1109/ICASIC.2005.1611405
