DocumentCode
3469309
Title
Design and verification of CMOS HSTL buffers - YF/spl I.bar/HSTL018
Author
Gao, Shaoquan ; Chen, Jihua ; Ma, Jianwu ; Liu, Ting
Author_Institution
Sch. of Comput. Sci., Nat. Univ. of Defense Technol., Changsha
Volume
2
fYear
2005
fDate
24-0 Oct. 2005
Firstpage
621
Lastpage
624
Abstract
HSTL level standard is technology for high-speed data transmission. Based on the analysis of applications, a couple of I/O buffers named YF_HSTL018, which are fully complied with HSTL level specification, are designed. The layout of the circuit is also realized. Through the Hspice simulation and chip test, good performance of the I/O buffers is demonstrated
Keywords
CMOS logic circuits; buffer circuits; logic design; CMOS HSTL buffers; HSTL level specification; Hspice simulation; YF_HSTL018 I/O buffers; high speed transceiver logic; high-speed data transmission; Bonding; CMOS logic circuits; CMOS technology; Circuit simulation; Circuit testing; Coupling circuits; MOSFET circuits; Resistors; Transconductance; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location
Shanghai
Print_ISBN
0-7803-9210-8
Type
conf
DOI
10.1109/ICASIC.2005.1611405
Filename
1611405
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