A 5GHz CMOS monolithic fractional-N frequency synthesizer

Author

Weilun Shen ; Kangmin Hu ; Xiaofeng Yi ; Ye Zhou

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

Volume

2

fYear

2005

fDate

24-27 Oct. 2005

Firstpage

626

Lastpage

629

Abstract

A 5GHz monolithic fractional-N frequency synthesizer is implemented in 0.18-μm CMOS technology. In this frequency synthesizer, the center frequency of VCO is twice that of the required LO frequency and the quadrature LO is generated through a divide-by-2 circuit. A 3-b third-order ΔΣ modulator is employed to randomize the division ratio and the phase noise performance is improved. Simulation result shows that the phase noise of the whole frequency synthesizer is less than -125dBc/Hz (3MHz) and the settling time is 25μs. Having a frequency resolution of 8Hz, the frequency synthesizer meets the specifications of WLAN 802.11b/g and Bluetooth. The chip area is 1 mm ×1.2mm and the current consumption is 30mA under a supply voltage of 1.8V.

Keywords

CMOS integrated circuits; MMIC oscillators; delta-sigma modulation; frequency synthesizers; phase locked loops; voltage-controlled oscillators; 0.18 micron; 1.8 V; 25 mus; 30 mA; 5 GHz; CMOS fractional-N frequency synthesizer; delta-sigma modulator; divide-by-2 circuit; phase noise; phase-locked-loop; voltage controlled oscillator; Bluetooth; CMOS technology; Circuit simulation; Delta modulation; Frequency conversion; Frequency synthesizers; Phase modulation; Phase noise; Voltage-controlled oscillators; Wireless LAN; CMOS; VCO; delta-sigma modulator; divide-by-2; frequency synthesizer; phase-locked-loop; quadrature;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2005. ASICON 2005. 6th International Conference On

Print_ISBN

0-7803-9210-8

Type

conf

DOI

10.1109/ICASIC.2005.1611406

Filename

1611406