The Fast Simulation Model of SRAM

Author

Zhou, Zhitao ; Zhang, Ganggang

Author_Institution

Dept. of Microelectron., Peking Univ.

fYear

2006

fDate

23-26 Oct. 2006

Firstpage

1333

Lastpage

1335

Abstract

With the development of microprocessor, large-storage and high-speed memories are required to keep up with it. Since the conventional simulation of memory is extremely time-consuming, a new performance model focusing on fast delay simulation of SRAM is presented in this paper. This simulation model is accurate and fast, validated by cadence simulation tool, it effectively solves the simulation difficulties of SRAMs with large storage and tremendously decreases the design cycle of SRAM, consequently, improves the design efficiency. Furthermore, we could use this simulation model to forecast the access time of large memories and get relatively good results

Keywords

SRAM chips; delays; electronic engineering computing; integrated circuit modelling; SRAM; cadence simulation tool; fast delay simulation; high-speed memory; large memory access time; large-storage memory; Circuit simulation; Decoding; Delay effects; Microelectronics; Microprocessors; Predictive models; Propagation delay; Random access memory; Time measurement; Transmission line theory;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306152

Filename

4098400