Title :
A way of enhancing test quality and restraining the increase of test cost for deep sub-micron integrated circuits
Author :
Du, Jun ; Zhao, Yuanfu ; Yu, Lixin
Author_Institution :
Beijing Microelectron. Technol. Inst.
Abstract :
Enhancing test quality and restraining test cost are two main topics in the domain of test and design for testability of deep sub-micron integrated circuits. This paper presents a multi-fault oriented test and DFT resolution scheme for DSM IC. The scheme can enhance the test quality of deep sub-micron chips by using a test suite consisted of stuck-at fault test, delay fault test and delta-IDDQ test. And it can restrain the increase of test cost by adopting a special ATPG strategy to reduce scan-based stuck-at test patterns. A design paradigm of 0.18 mum MCU to which the scheme is applied is also introduced in the paper
Keywords :
automatic test pattern generation; design for testability; fault simulation; integrated circuit testing; 0.18 micron; ATPG strategy; DFT resolution scheme; automatic test pattern generation; deep sub-micron integrated circuits; delay fault test; delta-IDDQ test; design for testability; multifault oriented test; scan-based stuck-at test patterns; stuck-at fault test; test cost; test quality enhancement; Automatic test pattern generation; Circuit faults; Circuit testing; Costs; Delay effects; Design for testability; Integrated circuit technology; Integrated circuit testing; Manufacturing; Test pattern generators;
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location :
Shanghai
Print_ISBN :
0-7803-9210-8
DOI :
10.1109/ICASIC.2005.1611417
