The implementation method about verifying to VLIW DSP

Microprocessor cores are a big challenge in the verification field because of their complexity and specific applications. Simulation-based test vector generator muGP can generate test set more efficiently than a random approach without need of skilled engineers. In this paper, we establish our verification of a 9-stage pipelined DSP with VLIW architecture on assistance of a test program generator. By adding a few manual test vectors statement coverage can attain up to 99.9%. This result shows the feasibility and effectiveness of our method