Study on analyzing and modeling of delay activity for digital circuit

A novel modeling method of longest path detecting for signal transmission and delay time computing of logic circuit is proposed in this paper. The method is based on graph theory so that it is quite simple. This paper introduces matrixes based on the circuit´s neighborhood graph, which is a labeled and directed graph G, 2-tuple G (V, E). The gate-level circuit is first transformed into a directed acyclic graph in which the gates appear as edges with certain option value and the signals correspond to the nodes marked with number. The neighborhood graph is then mapped onto a conjunction matrix. The novel method could also give the formulas of calculating the delay time as well as detecting the longest path of delay.