FBDD: a folded logic synthesis system

Despite decades of efforts and successes in logic synthesis, algorithm runtime has rarely been taken as a first class objective in research. As design complexity soars and million gate designs become common, as deep submicron effects dominate and frequently invoking logic synthesis within a low-level physical design environment, or a high-level architectural exploration environment become mandatory, it becomes necessary to revisit the fundamental logic synthesis infrastructure and algorithms. In this paper, we demonstrate FBDD, an open sourced, binary decision diagram (BDD) based logic synthesis package, which employs several new techniques, including folded logic transformations and two-variable sharing extraction. Towards the goal of scaling logic synthesis algorithms, we show that for standard benchmarks, and for field programmable gate array (FPGA) technology, FBDD can produce circuits with comparable area with commercial tools, while running one order of magnitude faster