FPGA implementation of image rotation using modified compensated CORDIC

Rotation is a basic operation for image processing, and the complexity of its computation is considered as the key problem of the implementation of real-time visual system. This paper proposes a novel architecture based on modified compensated CORDIC and bilinear interpolation algorithms in a recursive and folded way. The proposed modified compensated CORDIC algorithm compensates the scale factor in parallel with angle rotations, expands the convergence range to entire 2pi and avoids pre- and post- rotations. The detailed architecture for image rotation is modeled by Verilog and implemented in Xilinx FPGA. Experiment results show that the proposed CORDIC algorithm has the lowest computational complexity and the architecture for real-time image rotation has lower hardware cost and power consumption