Design and implementation of reconfigurable AES IP core using FPGAs

In this paper, a high-performance and dynamic reconfigurable AES IP core is presented, which provides full support for encryption/decryption models and 128/192/256-bit key lengths. To save the hardware cost, sharing technique is adopted to key modules and dynamic reconfigurable S-boxes according to operation models. Compared with traditional schemes, the reconfigurable scheme not only provides full hardware support for the AES implementing modes and three possible key sizes, but also reduces the required logic elements to 43% and the required memory bits to 17% on equivalent frequency. This one also provides a better secure and flexible scheme for different requirements