DocumentCode
3469770
Title
The art of sampling reduction
Author
Keung Hui ; Mou, Jinyu
Author_Institution
Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan
fYear
2013
fDate
6-6 Sept. 2013
Firstpage
1
Lastpage
5
Abstract
This paper examines impacts of metrology delays on the system performances of advanced process control solutions in semiconductor manufacturing. The analysis establishes a first step in any assessment of sampling reduction, a persistent notion amid the relentless drives of cutting production costs. We show that metrology delays deteriorate system performances with increased variances but retain system stability at large. The task on sampling reduction is finally casted as an art of business decision.
Keywords
cost reduction; measurement; process control; sampling methods; semiconductor device manufacture; metrology delay; process control solutions; production cost cutting; sampling reduction; semiconductor manufacturing; Art; Delays; advanced process control; gain mismatch; metrology delay; system stability;
fLanguage
English
Publisher
ieee
Conference_Titel
e-Manufacturing & Design Collaboration Symposium (eMDC), 2013
Conference_Location
Hsinchu
Type
conf
DOI
10.1109/eMDC.2013.6756047
Filename
6756047
Link To Document