A minimum-distance search circuit using dual-line PWM signal processing and charge-packet counting techniques

Author

Nagata, M. ; Yoneda, T. ; Nomasaki, D. ; Sano, M. ; Iwata, A.

Author_Institution

Fac. of Eng., Hiroshima Univ., Japan

fYear

1997

fDate

8-8 Feb. 1997

Firstpage

42

Lastpage

43

Abstract

This CMOS minimum distance search circuit (MDS) realizes pattern matching engines for multi-media and intelligent processing systems. The chip executes highly-parallel computation of Manhattan distances between an input vector and stored multiple reference vectors, and search of the minimum distance among them. Two novel circuit techniques are based on pulse width modulation (PWM) analog-digital merged circuits.

Keywords

CMOS integrated circuits; mixed analogue-digital integrated circuits; multimedia computing; pattern matching; pulse width modulation; CMOS; Manhattan distances; analog-digital merged circuits; charge-packet counting techniques; dual-line PWM signal processing; highly-parallel computation; input vector; intelligent processing systems; minimum-distance search circuit; multimedia processing systems; pattern matching engines; pulse width modulation; stored multiple reference vectors; CMOS technology; Counting circuits; Frequency; Pipeline processing; Pulse width modulation; Semiconductor device measurement; Signal processing; Switches; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3721-2

Type

conf

DOI

10.1109/ISSCC.1997.585252

Filename

585252