VLSI dynamically reconfigurable hardware for finite state machine design and analyses

Some applications in memory can be constrained by memory bandwidth and memory cost, area this paper proposes a transformation of the application into a one-bit FSM. And then when the finite state machine is very large one way to improve the area and delay efficiently is to break down the large finite state machine into many smaller machines and the area efficiency can be improved if few machines are active simultaneously in the pipelined architecture. This can be achieved when using dynamically reconfiguration to map several sub machines onto the same hardware. This paper presents an efficient VLSI realization for the dynamically reconfiguration after break down. Different results experimental are presented with different sizes of the configurable parts and the features of our hardware with real application such as IP lookup engine database RIPE