55GCPS CAM using 5b analog flash

Author

Kramer, A. ; Canegallo, R. ; Chinosi, M. ; Doise, D. ; Gozzini, G. ; Navoni, L. ; Rolandi, P.L. ; Sabatini, N.

Author_Institution

SGS-Thomson Microelectron., Agrate Brianza, Italy

fYear

1997

fDate

8-8 Feb. 1997

Firstpage

44

Lastpage

45

Abstract

An analog CAM based on analog flash technology contains 256k computing nodes, organized into 4k rows of 64 synapses each, and is able to process in parallel the best match based on Manhattan distance between a 64-dimensional input vector and all 4b stored reference vectors. Each computing node is capable of storing and matching 5b data (1.28Mb total storage), making this CAM well suited to problems in pattern recognition that require limited precision. The chip uses analog flash technology for data storage, programmable on-chip references, and offset compensation.

Keywords

analogue storage; content-addressable storage; memory architecture; pattern matching; 1.28 Mbit; Manhattan distance; analog CAM; analog flash technology; offset compensation; pattern recognition; programmable on-chip references; stored reference vectors; synapses; Analog computers; CADCAM; Circuits; Computer aided manufacturing; Computer architecture; Concurrent computing; Matrix converters; Microelectronics; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3721-2

Type

conf

DOI

10.1109/ISSCC.1997.585253

Filename

585253