Research on generating the constants T[i] of MD5 algorithm based on FPGAs

This paper critically analyze the character of the constant T[i] of MD5 hash algorithm. Unlike previous works which rely on look-up tables to store constant T[i], the proposed design employs combinational logic only. As a direct consequence, the unbreakable delay incurred by look-up tables in the conventional approaches is eliminated, which is efficient and secure, suitable for FPGAs implementation. The new design introduces the feedback shift register and the nonlinear feedback shift register to generate the constant T[i] instead of storing directly based on FPGAs. To compare with traditional schemes, experiment results show that the required logic elements reduce 84% and the output´s delay reduces 38%. Finally, this paper presents a good research trend for resolving the storage in hardware implementation using FPGAs