Title :
A 256 Mb SDRAM using a register-controlled digital DLL
Author :
Hatakeyama, A. ; Mochizuki, H. ; Aikawa, T. ; Takiia, M. ; Ishii, Y. ; Tsuboi, H. ; Fujioka, S. ; Yamaguchi, S. ; Koga, M. ; Serizawa, Y. ; Nishimura, K. ; Kawabata, K. ; Okajima, Y. ; Kawano, M. ; Kojima, H. ; Mizutani, K. ; Anezaki, T. ; Hasegawa, M. ;
Author_Institution :
Fujitsu Labs. Ltd., Kawasaki, Japan
Abstract :
This 256 Mb synchronous DRAM with 1 ns clock access is stable against temperature, voltage, and process variation by use of an innovative register-controlled delay locked loop (RDLL). Unlike most conventional high-density DRAMs, the bit-lines are placed above the storage capacitors in this DRAM to relax design rules of the core area. The noise issues are analyzed and resolved to help implement the technology in mass production of 0.28 to 0.24 /spl mu/m 200 MHz DRAMs.
Keywords :
CMOS memory circuits; DRAM chips; circuit stability; delay circuits; integrated circuit noise; 0.24 to 0.28 micron; 1 ns; 200 MHz; 256 Mbit; SDRAM; delay locked loop; high-density dynamic RAM; noise; register-controlled digital DLL; synchronous DRAM; Capacitors; Circuits; Clocks; Delay lines; Quantization; SDRAM; Shift registers; Temperature; Timing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3721-2
DOI :
10.1109/ISSCC.1997.585266
