DocumentCode :
3470054
Title :
3D placement algorithm considering vertical channels and guided by 2D placement solution
Author :
Liu, Guilin ; Li, Zhuoyuan ; Zhou, Qiang ; Hong, Xianlong ; Yang, Hannah Honghua
Author_Institution :
Graduate Sch., Tsinghua Univ., Beijing, China
Volume :
2
fYear :
2005
fDate :
24-27 Oct. 2005
Firstpage :
787
Lastpage :
791
Abstract :
3D integration is a potential solution to solve complex problem caused by interconnect delay that dominates the total budgets. In this placer, we bring up a 3D placement algorithm and focus on two issues: the effect of vertical channels and the constraint that cells can not leave the plane after assigned to it. Firstly, we develop an algorithm to verify the effect of vertical channels in wire length optimization. Secondly, because of the constraint presented above the placement quality is restricted badly. We research the possibility of improving placement quality by importing an initial solution. Experiments on a set of benchmarks prove our algorithm efficient and effective.
Keywords :
circuit optimisation; integrated circuit design; integrated circuit interconnections; logic partitioning; 2D placement solution; 3D integration; 3D placement algorithm; interconnect delay; placement quality; vertical channels; wire length optimization; Assembly; Computer science; Constraint optimization; Delay; Integrated circuit interconnections; Moore´s Law; Packaging; Partitioning algorithms; Process planning; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Print_ISBN :
0-7803-9210-8
Type :
conf
DOI :
10.1109/ICASIC.2005.1611446
Filename :
1611446
Link To Document :
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